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73s8023c smart card interface simplifying system integration? data sheet april 2009 rev. 1.5 ? 2009 teridian semiconductor corporation 1 description the teridian 73s8023c is a low - power, high efficiency, single smart card interface ic suitable for 3v and 5v cards . it provides full electrical compliance with iso - 7816 - 3 and emv 4.0 (emv2000) specifications. hardware sup port for any type of synchronous ca rds (memory cards) is provided. interfacing with the system controller is done through the control bus; composed of digital inputs to control the interface, and one interrupt output to inform the system controller of the card presence and faults . data exchange with the card is managed from the system controller using the i/o line (and eventually the auxiliary i/o lines). a chip select input allows multiple 73s8023c ics to share the same control bus . when chip select is set low, the host microcontroller inputs are latched and outputs are taken to a high impedance state. the card clock signal can be generated by an on - chip oscillator using an external crystal or by connecting an external clock signal. the 73s8023c device incorporates an iso - 7816 - 3 activation/deactivation sequencer that controls the card signals . emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. the 73s8023c requires only a single 2.7 v to 3.6 v power supply, and features a high - efficiency embedded dc - dc converter . this architecture, plus a power down digital input that allow placing the ic in a very low - power mode making the 73s8023c particularly suitable for low - power applications (cell - phones, pdas, payphones, hand - held pos terminals). advantages ? supports both synchronous and asynchronous smart cards ? replacement for tda8002, with up to 600 mw in power savings (@ emv iccmax condition) ! ? the inductor - based dc - dc converter provides highe r current and efficiency ? ideal for battery - powered applications ? suitable for high current cards and sams: (100 ma max) ? single 2.7 v to 3.6 v power supply allows removal of 5 v from the system ? power down mode: 2 a typical ? package: small format (5x5mm) 32 - qfn features ? card interface: ? complies with iso - 7816 - 3, emv 4.0 ? a dc - dc converter provides 3v / 5v to the card from an external power supply input ? high - efficiency converter: > 80% @ v dd =3.3 v, v cc =5 v and i cc ? up to 100 ma supplied to the card = 65 ma ? iso- 7816 - 3 activation / deactivation sequencer with e mergency automated deactivation ? protection includes 2 voltage supervisors which detect voltage drops on card v cc and on v dd ? the v power supply dd ? true over - current detection (150 ma max.) voltage supervisor threshold value can be externally adjusted ? 2 card detection inputs, 1 for either possible switch configuration ? full support of synchronous cards ? system controller interface: ? 3 digital inputs control the card ac tivation / deactivation, card reset and card voltage ? 3 digital inputs control the card clock (division rate and card clock source selection) ? 1 digital output, interrupt to the system controller, allows the system controller to monitor the card presence and faults ? 1 power down digital input (places the 73s8023c in a very low - power mode (card deactivated) ? 1 chip select digital input for parallel operation of several 73s8023c ics. ? 1 external clock input (strobe), used for synchronous operation ? 1 digital output clock, buffered version of signal on xtalin ? crystal oscillator or host clock (xtalin), up to 27 mhz ? power supply: v dd ? 6 kv esd protection on the card interface 2.7 v to 3.6 v applications ? point of sales and transaction terminals ? payphones ? set - top - boxe s, dvd / hdd recorders ? payment card interfaces in portable devices (pdas, mobile phones) downloaded from: http:///
73s8023c data sheet ds_8023c_019 2 rev. 1.5 functional diagram figure 1 : 73s8023c block diagram icc i/o buffers vdd voltage supervisor voltage reference xtal osc clock generation digital circuitry & fault logic v dd fault v cc fault int_clk vdd vdd vcc rstclk pres pres xtalin xtalout clkdiv1clkdiv2 gnd temp fault nc 2930 31 2 6 4 6 7 910 11 12 13 15 14 20 19 18 17 26 24 23 22 28 27 iso-7816-3 sequencer r-c osc. dc-dc converter icc reset buffer icc clock buffer over temp pwrdn i/o aux1 aux2 iouc aux1uc aux2uc vddf_adj rstin cmdvcc 5v/3v off 5 gnd 1 3 lin 6 21 gnd i cc fault clkout 32 8 cs clksel 16 strobe 25 downloaded from: http:///
ds_8023c_019 7 3s8023c data sheet rev. 1.5 3 table of contents 1 pin de scription ................................................... ................................................... .............................. 5 1.1 card interface ................................................... ................................................... ......................... 5 1.2 miscellaneous inputs and outputs ................................................... ............................................. 5 1.3 power supply and ground ................................................... ................................................... ...... 5 1.4 microcontroller interface ................................................... ................................................... ......... 6 2 system controller interface ................................................... ................................................... ......... 7 3 oscillator ................................................... ................................................... ........................................ 8 4 dc - dc converter C card power supply ................................................... ....................................... 8 5 voltage supervision ................................................... ................................................... ..................... 9 6 power down ................................................... ................................................... ................................. 10 7 over - temperature monitor ................................................... ................................................... ......... 10 8 activation and deactivation ................................................... ................................................... ....... 11 8.1 activation sequence (synchronous mode) ................................................... ............................. 11 8.2 deactivation sequence (synchronous mode) ................................................... ......................... 11 8.3 activation sequence (asynchronous mode) ................................................... ............................ 12 8.4 deactivation sequence (asynchronous mode) ................................................... ....................... 14 9 off and fault detection ................................................... ................................................... ............ 14 10 i/o circuitry and timing ................................................... ................................................... ............. 15 11 typical application schematic ................................................... ................................................... .. 17 12 electrical specification ................................................... ................................................... ............... 18 12.1 absolute maximum ratings ................................................... ................................................... .. 18 12.2 recommended operating conditions ................................................... ...................................... 18 12.3 package thermal parameters ................................................... ................................................. 18 12.4 card interface characteristics ................................................... ................................................. 19 12.5 digital signals ................................................... ................................................... ....................... 22 12.6 dc characteristics ................................................... ................................................... ................ 23 12.7 voltage / temperature fault detection circuits ................................................... ....................... 23 13 mechanical drawing (32 - qfn) ................................................... ................................................... ... 24 14 package pin designation (32 - qfn) ................................................... ............................................. . 25 15 ordering information ................................................... ................................................... .................. 26 16 related documentation ................................................... ................................................... .............. 26 17 contact information ................................................... ................................................... .................... 26 revision history ................................................... ................................................... .................................. 27 downloaded from: http:///
73s8023c data sheet ds_8023c_019 4 rev. 1.5 figures figure 1: 73s8023c block diagram ................................................... ................................................... ....... 2 figure 2: power down mode operation: cs = high ................................................... ................................. 10 figure 3: activation sequence C synchronous mode ................................................... .............................. 11 figure 4: synchronous deactivation operation C cksel = high ................................................... ............ 12 figure 5: asynchronous activation sequence C rstin low when cmdvcc goes low ......................... 13 figure 6: asynchronous activation sequence C timing diagram #2 ................................................... ...... 13 figure 7: asynchronous deactivation sequence ................................................... ..................................... 14 figure 8: timing diagram C management of the interrupt line off ................................................... ....... 15 figure 9: i/o and i/ouc state diagram ................................................... ................................................... 16 figure 10: i/o C i/ouc delays timing diagram ................................................... ....................................... 16 figure 11: 73s8023c C typical ap plication schematic ................................................... ........................... 17 figure 12: dc C dc converter efficiency (v cc = 5 v) ................................................... ............................. 20 figure 13: dc C dc converter efficiency (v cc = 3 v) ................................................... ............................. 20 figure 14: 32 - qfn mechanical drawing ................................................... .................................................. 24 figure 15: 32 - qfn 73s8023c pin out ................................................... ................................................... . 25 table table 1: choice of vcc pin capacitor ................................................... ................................................... .... 8 downloaded from: http:///
ds_8023c_019 7 3s8023c data sheet rev. 1.5 5 1 pin description 1.1 card interface name pin description i/o 9 card i/o : data signal to/from card. includes a pull - up resistor to v cc. aux1 11 aux1: auxiliary data signal to/from card. includes a pull - up resistor to v cc. aux2 10 aux2 : auxiliary data signal to/from card. includes a pull - up resistor to v cc. rst 14 card reset : p rovides reset (rst) signal to card. clk 13 card clock : p rovides clock (clk) signal to card. the rate of this clock is determined by crystal oscillator frequency and clkdiv selections. pres 7 card presence switch : a ctive high indicates card is present . includes a pull - down current source. pres 6 card presence switch : a ctive low indicates card is present . includes a pull - up current source. vcc 15 card power supply: l ogically controlled by sequencer, output of dc - dc converter . requires an external filter capacitor to the card gnd. gnd 12 card ground. 1.2 m iscellaneous inputs and outputs name pin description xtalin 23 crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. xtalout 24 crystal oscillator output: connected to crystal. left open if xtalin is being used as external clock input. vddf_adj 17 v dd fault threshold adjustment input: this pin can be used to adjust v ddf value (that controls deactivation of the card). must be left open if unused. nc 4 non - connected pin. must be left open . 1.3 p ower supply and ground n ame pin description vdd 3, 20 system controller interface supply voltage: supply voltage for internal power supply and dc - dc converter power supply source . gnd 1 dc - dc converter ground. gnd 21 digital ground. lin 2 external inductor. connect external inductor from pin 2 to v dd . keep the inductor close to pin 2. downloaded from: http:///
73s8023c data sheet ds_8023c_019 6 rev. 1.5 1.4 m icrocontroller i nterface name pin description cmdvcc 18 command v cc (negative assertion) : logic low on this pin causes the dc - dc converter to ramp the v cc supply to the card and initiates a card activation sequence . 5v/ #v 31 5 volt / 3 volt card selection : logic one selects 5 volts for v cc and card interface, logic low selects 3 volt operation . when the part is to be used with a single card voltage, this pin should be tied to either gnd o r v dd . however, it includes a high impedance pull - up resistor to default this pin high (selection of 5v card) when unconnected pwrdn 5 power down control input : active high. when power down (pd) mode is activated, all internal analog functions are disabled to place the 73s8023c in its lowest power consumption mode . the pd mode is allowed only out of a card session (pwrdn high is ignored when cmdvcc = 0). must be tied to ground when power down function is not used. clkdiv1 clkdiv2 29 30 sets the divide ratio from the xtalin oscillator (or external clock input) to the card clock. these pins include pull - down resistors. clkdiv1 clkdiv2 c lock rate 0 0 xtalin/8 0 1 xtalin/4 1 1 xtalin/2 1 0 xtalin off 22 interrupt signal to the processor : active lo w. multi - function indicating fault conditions and card presence . open drain output configuration ; i t includes an internal 20 k pull - up to v dd. rstin 19 reset input : this signal controls the rst signal to the card. i/ouc 26 system controller data i/o to/from the card. includes internal pull - up resistor to v dd. aux1uc 27 system controller auxiliary data i/o to/from the card . includes internal pull - up resistor to v dd. aux2uc 28 system controller auxiliary data i/o to/from the card . includes internal pull - up resistor to v dd. cs 8 when cs = 1, the control and signal pins are configured normally. when c s is set low, signals c mdvcc, rstin, pwrdn, 5v/#v, clkdiv1, clkdiv2, clksel are latched. i/ouc, aux 1uc, and aux2uc are set to high impedance pull - up mode and wont pass data to or from the smart card. off output is tri - stated. clksel 16 selects clk and rst operational mode. when clksel is low (default), the circuit is configured for asynchronous card operation and the sequencer manages the control of clk and rst. when clksel is high, the signal clk is a buffered copy of strobe and the signal rst is directly controll ed by rst in. strobe 25 when clksel = 1, the signal clk is controlled directly by strobe. clkout 32 clkout is the buffered version of the signal on pin xtalin. downloaded from: http:///
ds_8023c_019 7 3s8023c data sheet rev. 1.5 7 2 system controller interface ? the cs (chip select) input allows multiple devices to operate in parallel. when cs is high, the system interface signals operate as described. when cs is taken low, the sy stem interface signals are latched internally. the pins i/ouc, aux1uc, and aux2uc are weakly pul led up and the off signal is put into a high impedance stat e. ? the clksel signal selects between synchronous and asynchronous operation. when clksel is low, asynchronous operation is selected. when clksel is high, synchronou s operation is selected. ? d igital inputs allow direct control of the card interface from the host as f ollows: ? pin cmdvcc : when set low, starts an activation sequence if a card is present . ? pin 5v/ #v : defines the card voltage . ? the card i/o and reset signals have their corresponding controller i/os to be connected directly to the host: ? pin rstin: controls the card rst signal. when enabled by the sequencer, rst is equal to rstin for both synchronous and asynchronous modes. ? pin i/ouc: data transfer to card i/o contact . ? pins aux1uc and aux2uc (auxiliary i/o lines associated to the auxili ary i/os which are connected to the c4 and c8 card connector contacts) . ? two digital inputs control the card clock frequency division rate: clkdiv1 and c lkdiv2 define the card clock frequency from the input clock frequency (crystal or external clock) . the division ra te is defined as follows: clkdiv2 clkdiv1 clk 0 0 ? xtal 0 1 xtal 1 0 ? xtal 1 1 ? xtal when the division rate is equal to 1 (clkdiv2 = 0 and clkdiv1 = 1 ), the duty - cycle of the card clock depends on the duty - cycle and waveform of the signal applied on the pin xtalin . when other division rates are used, the 73s8023c circuitry guarantees a duty - cycle in the range 45% to 55%, conforming to iso - 7816 - 3 and emv 4.1 specifications . ? interrupt output to the host: as long as the card is not activated, the off pin informs the host about the card presence only (l ow = n o card in the reader) . when cmdvcc is set low (card activation sequence requested from the host), a low level on off means a fault has been detected (e.g. card removed l during a card session, or voltage fault, or thermal / over - current fault) that automatically initiates a deactivation sequence. ? power down: the pwrdn pin is a digital input that allows the host controller to put the 73s8023c in its power down state . this pin can only be activated outside of a card session . ? the clkout signal is a buffered output of the signal applied to the xtalin pin wheth er it is an external clock source or it is configured as a crystal oscillator. c lkout can be used when using multiple 73s8023c devices to share a single clock signal. ? the strobe input directly drives the smart card clk signal when operating in synchronous mode. strobe is ignored in asynchronous mode. downloaded from: http:///
73s8023c data sheet ds_8023c_019 8 rev. 1.5 3 oscillator the 73s8023c device has an on - chip oscillator that can generate the smart card clock using an external crystal (connected between the pins xtalin and xtalout) to set the oscil lator frequency. when the card clock signal is available from another source, it can be connected to the pin xtalin, and the pin xtalout should be left unconnected. signal clkout is the buffered version of the signa l on xtalin. 4 dc - dc converter C card power supply an internal dc - dc converter provides the card power supply . this converter is able to provide either 3 v or 5 v card voltage from the power supply applied on the v dd pin. the digital iso - 7816 - 3 sequencer controls t he converter . card voltage selection is carried out by the digital input 5v/ #v . the circuit is an inductive step - up converter/regulator. the external components required are 2 filter capacitors on the power - supply input v dd ( next to the lin pin, 100 nf + 10 f), an inductor, and an output filter capacitor on the card power supply v cc . the circuit performs regulation by activating the step - up operation when v cc is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage and the input supply v dd is less than the set point for v cc . when v dd is greater than the set point for v cc (v dd = 3.6 v, v cc =3 v) the circuit operates as a linear regulator. depending on the inductor values, the voltage converter can provide current on v cc as high as 100 ma. the circuit provides over - current protection and limits i cc to 150 ma. when an over - current condition is sen sed, the circuit initiates a deactivation sequence from the control logic and reports back to the host controller a fault on the interrupt output off . choice of the inductor the nominal inductor value is 10 h, rated for 400 ma. the inductor is connected between lin (pin 2) and the v dd supply voltage . the inductor value can be optimized to meet a particular configuration (i cc_ max ). the inductor should be located on the pcb as close as possible to the lin pin of the ic. choice of the v cc depending on the applications, the requirements in terms of both the v capacitor cc table 1 minimum voltage and the transient currents that the interface must provide to the card are different . shows the recommended capacitors for each v cc table 1 : choice of vcc pin capaci tor power supply configuration and applicable specification. specification requirement application s p e c if ic a t io n min v cc ma x transient current c harge voltage a llowed during transient c urrent capacitor type capacitor value emv 4.1 4.6 v 30 nas x5r/x7r w/ esr < 100 m ? 3.3 f iso - 7816 -3 4.5 v 20 nas 1 f nds 4.6 5 v 40 nas 3.3 f downloaded from: http:///
ds_8023c_019 7 3s8023c data sheet rev. 1.5 9 5 voltage supervision two voltage supervisors constantly check the presence of the voltages v dd and v cc . a card deactivation sequence is triggered upon a fault detected by these voltage supervisors. the digital circuitry is powered by the power supply applied on the vdd pin . v dd also defines the voltage range for the interface with the system controller . the v dd voltage supervisor is also used to initialize the iso - 7816 - 3 sequencer at power - on, and also to deactivate the card at power - off or upon a fault . the voltage threshold of the v dd voltage supervisor is internally set by default to 2.3 v nominal . however, it may be desirable, in some applications, to modify this threshold value . the pin vddf_adj (pin 17) is used to connect an external resistor r ext to ground to raise the v dd fault voltage to another value, v ddf . the resistor value is defined as follows: r ext = 180 k /(v ddf an alternative (more accurate) method of adjusting the v - 2.33) dd figure 11 : 73s8023c C typical application schematic fault voltage is to use a resistive network of r3 from the pin to supply and r1 from the pin to ground (see ). in order to set the new threshold voltage, the equivalent resistance must be determined. this resistance value will be designated kx. kx is defined as r1/(r1 +r3). kx is calculated as: kx = (2.649 / v th ) - 0.6042 where v th is the desired new threshold voltage. to determine the values of r1 and r3, use the following form ulas: r3 = 72000 / kx r1 = r3*(kx / (1 C kx)) taking the example above, where a v dd fault threshold voltage of 2.7 v is desired, solving for kx gives: ? kx = ( 2.649 / 2.7) - 0.6042 = 0.377 solving for r3 gives: ? r3 = 72000 / 0.377 = 191 k ? . solving for r1 gives: ? r1 = 191000 *(0.377 / (1 C 0.377)) = 115.6 k ? . using standard 1 % resistor values gives r3 = 191 k ? and r1 = 115 k ?. these values give an equivalent resistance of kx = 0.376, a 0.3% error. using 1% external resistors and a parallel resistance of 72 k ohms will result in a +/ - 6% tolerance in the value of vdd fault. the sources of variation due to integrated circuit process variations and mismatches include the internal reference voltage (less than +/ - 1%), the internal comparator hysteresis an d offset (less than +/ - 1.7% for part - to - part, processing and environment), the internal resistor value mismatch and value variations (less than 1.8%), and the external resistor values (1%). if the 2.3 v default threshold is acceptable, this pin must be left unconnected. downloaded from: http:///
73s8023c data sheet ds_8023c_019 10 rev. 1.5 6 power down a power down function is provided via the pwrdn pin ( a ctive h igh) . when activated, the power down (pd) mode disables all the internal analog functions, including the card analog interf ace, the oscillators and the dc - dc converter, to put the 73s8023c in its lowest power consumption mode . pd mode is only allowed in the deactivated condition (out of a card session, when the cmdvcc signal is driven high from the host controller). t he host controller invokes the power down state when it is desirable to save pow er. the signals pres and pres remain functional in pd mode such that a card insertion sets off high. the micro - controller must then set pwrdn low and wait for the internal stabilization time prio r to starting any card se ssion (prior to turning cmdvcc low) . resumpti on of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators and reset of the circuitry) after pwrdn is set low. no card activat ion should be invoked during this 10 ms time per iod . if a card is present, off can be used as an indication that the circuit has completed its recovery from power - down state. off will go high at the end of the stabilization period . should cmdvcc go low during pwrdn = 1, or within the 10 ms internal s tabilization / reset time, it will not be taken into account and the card interface will remain inactive . since cmdvcc is taken into account on its edges, it should be toggled high and low again after the 10 ms to activate a card . figure 2 illustrates the sequencing of the pd and normal modes. pwrdn must be conn ected to gnd if the power down function is not used. figure 2 : power down mode operation: cs = high 7 over -t emperature monitor a built - in detector monitors die temperature . when an over - temperature condition occurs , a card deactivation sequence is initiated, and an error or fault condition is reported t o the system controller. pres off pwrdn internal rc osc cmdvcc off follows pres regardless of pwrdn pwrdn during a card session has no effect after setting pwrdn = 0, the controller must wait at least 10ms before setting cmdvcc =0 emv / iso deactivation time ~= 100 us ~10ms pwrdn has effect when the cardi s deactivated downloaded from: http:///
ds_8023c_019 73s8023c data sheet rev. 1.5 11 8 activation and deact ivation 8.1 activation sequence (synchronous mode ) the 73s8023c smart card interface ic has an internal ~10 ms delay at power - on reset or on application of v dd > v ddf 1. cmdvcc is set low. . no activation is allowed at this time. cmdvcc (edge triggered) must then be set low to act ivate the card. the following steps list the activation sequence and the timing of the card control signals when the system controller sets cmdvcc low: 2. turn on v cc and i/o (aux1, aux2) to reception mode at the end of (t act 3. rst is a c opy of rstin and clk is a copy of strobe after (t ). 1 ). figure 3 : activation sequence C synchronous mode 8.2 deactivation sequence (synchronous mode) deactivation is initiated either by the system controller by setting the cmdvcc high, or automatically in the event of hardware faults . hardware faults are over - current, overheating, v dd 1. rst goes low at time t fault and card extraction during the session and are indicated to the system controller by the fall of off . the following steps list the deactivation sequence and the timing of the card control signals when the system controller sets the cmdvcc high or a fault condition sets off low: 1 2. clk stops low at time t . 2 3. i/o goes low at time t . 3 4. v . out of reception mode. cc is shut down at time t 4 . after a delay t 5 (discharge of the v cc capacitor), v cc is low. cmdvcc vcc io clk rstin t act t 1 rst strobe t act ~= 500 s t 1 > 0.5 s after t act , rst = rstin, clk = strobe downloaded from: http:///
73s8023c data sheet ds_8023c_019 12 rev. 1.5 cmdvcc vcc io off rstin rst strobe clk t 0 - deactivation starts after cm dv cc is set high or off falls due to card removal or fault t 4 - vcc is shut down ( note: host should set strobe low when cmdvcc is set high , otherwise clk may be truncated . clk truncation may occur if an off event is triggered ) t 3 - io falls approx 2 us after clk falls t 1 - rst falls approx . 0.5 us after deactivation begins t 2 - clk falls approx . 7.5 us after rst falls -- or -- t 0 t 1 t 2 t 3 t 5 t 4 t 5 - vcc goes to 0 after discharge of vcc capacitor , approx 100 us after deactivation begins figure 4 : synchronous de activation operation C cksel = high 8.3 activation sequence (a synchronou s mode ) the 73s8023c smart card interface ic has an internal 10 ms delay at power - on reset or upon application of v dd > v ddf 1. cmdvcc is set low. or upon exit of power down mode. the card interface may only be activated when off is high which indicates a card is present . no activation is allowed at this time. cmdvcc (edge triggered) must then be set low to activate the card. the following steps list the activation sequence and the timing of the card control signals when the system controller sets cmdvcc low while the rstin is low: 2. next, the internal v cc control circuit checks the presence of v cc at the end of t 1 . in normal operation, the voltage v cc to the card becomes valid during t 1 . if v cc does not become valid, then off goes low to report a fault to the system controller, and the power v cc 3. turn i/o (aux1, aux2) t o reception mode at the end of t to the card is turned off. 2 4. clk is applied to the card at the end of t . 3 5. rst is a copy of rstin after t . 4 . rstin may be set high before t 4 , however the seque ncer wont set rst high until 42000 clock cycles after the start of clk. downloaded from: http:///
ds_8023c_019 73s8023c data sheet rev. 1.5 13 figure 5 : asynchronous activation sequence C rst in low w hen c m d v c c goes l ow the following steps list the activation sequence and the timing of the card control signals when the system controller pulls the cmdvcc low while the rstin is high: 1. cmdvcc is set low. 2. next, the internal v cc control circuit checks the presence of v cc at t 1 . in normal operation, the voltage v cc to the card becomes valid during this time . if not, off goes low to report a fault to the system controller, and the power v cc 3. due to the fall of rstin at t to the card is turned off. 2 4. clk is applied to the card at the end of t , turn i/o (aux1, aux2) to reception mode. 3 5. rst is to be a copy of rstin after t after i/o is in reception mode. 4 . rstin may be set high before t 4 , however the sequencer wont set rst high until 42000 clock cycles after the start of clk. cmdvcc vcc io clk rstin t 1 t 2 t 3 t 4 rst t 1 = 0.510 ms (timing by 1.5mhz internal oscillator) t 2 = 1.5 s, i/o goes to reception state t 3 = > 0.5 s, clk active t 4 figure 6 : asynchronous activation sequence C timing diagram #2 42000 card clock cycles . time for rst to become the copy of rstin cmdvcc vcc io clk rstin t 1 t 2 t 3 t 4 rst t 1 = 0.510 ms (timing by 1.5 mhz internal oscillator) t 2 = 1.5 s, i/o goes to reception state t 3 0.5 s, clk starts t 4 42000 card clock cycles. time for rst to become the copy of rstin downloaded from: http:///
73s8023c data sheet ds_8023c_019 14 rev. 1.5 8.4 d eactivation sequence (a synchronous mode ) deactivation is initiated either by the system controller by setting cmdvcc high, or automatically in the event of hardware faults . hardware faults are over - current, overheating, v dd fault, v cc 1. rst goes low at the end of time t fault, and card extraction during the session. the following steps list the deactivation sequence and the timing of the card control signals when the system controller sets the cmdvcc high or off goes low due to a fault or card removal: 1 2. clk stops low at the end of time t . 2 3. i/o goes low at the end of time t . 3 4. v . out of reception mode. cc is shut down at the end of time t 4 . after a delay t 5 (discharge of the v cc capacitor), v cc is low. rst clk i/o vcc t 1 t 2 t 3 t 4 t 5 cmdvcc -- or -- off figure 7 : asynchronous deactivation sequence 9 off and f ault detection there are two cases for which the system controller can monitor the off signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. m oni t or i ng o ut s i d e a c a r d s e s s i on in this condition, cmdvcc is always high, off is low if the card is not present, and high if the card is present . because it is outside a card session, any fault detection will not act upon the off signal. no deactivation is required during this time. m oni t or i ng d ur i ng a c ar d s es s i o n cmdvcc is always low, and off falls low if the card is extracted or if any fault is detected . at the same time that off is set low, the sequencer starts the deactivation process . figure 8 shows the timing diagram for the signals cmdvcc , pres, and off during a card session and outside the card session: t 1 0.5 s, timing by 1.5 mhz internal oscillator t 2 7.5 s t 3 0.5 s t 4 0.5 s t 5 = depends on v cc filter capaci tor. t 1 + t 2 + t 3 + t 4 + t 5 ~= 100 s downloaded from: http:///
ds_8023c_019 73s8023c data sheet rev. 1.5 15 figure 8 : timing diagram C management of the interrupt line off 10 i/o circuitry and timing the i/o, aux1, and aux2 pins are in the low state after power - on reset and they are in the high state when the activation sequencer turns on the i/o reception state. see section 8 activation and deactivation for more details on when the i/o reception is on . the state of the i/ouc, aux1uc, and aux2uc pins is high after power - on reset . within a card session and when the i/o reception state is on, the first i/o line on which a falli ng edge is detected becomes the input i/o line and the other becomes the output i/o line . when the input i/o line rising edge is detected , both i/o lines return to their neutral state. figure 9 shows the state diagram of how the i/o and i/ouc lines are managed to becom e input or output . the delay between the i/o signals is shown in figure 10 . i n order to be compliant to the nd s specifications, a 27 pf capacitor must be added between pins i/o (c7) and gnd (c5) at the smart card connector. pres off cmdvcc vcc outside card session within card session off is low by card extracted off is low by any fault within card session downloaded from: http:///
73s8023c data sheet ds_8023c_019 16 rev. 1.5 neutral state i/ouc in i/o reception i/oicc in no yes no no no yes no yes i/o & not i/ouc i/ouc & not i/o i/ouc i/o yes yes figure 9 : i/o and i/ouc state diagram io iouc t io_hl t io_lh t iouc_hl t iouc_lh delay from i/ o to i/ouc: t io_hl = 100ns t io_lh = 25ns delay from i/ouc to i/o: t i/ouc_hl = 100ns t i/ouc_lh figure 10 : i/o C i/ouc delays timing diagram = 25ns downloaded from: http:///
73s8023c data sheet ds_8023c_019 rev. 1.5 17 11 typical application schematic 32qfn 73s8023c 14 38 6 7 1213 14 15 24 23 gnd nc vdd pres pres gnd clk rst vcc xtalout xtalin 2 lin 5 pwrdn cs 16 clksel 29 30 31 28 27 26 clkdiv1 clkdiv2 5v/3v aux2uc aux1uc i/ouc 25 strobe 32 clkout 17 18 19 20 21 22 vddf_adj cmdvcc rstin vdd gnd off 10 9 11 aux2 i/o aux1 see note 4 vdd pwrdn_from_uc y1 crystal c2 22pf c1 so7816=1uf, nds/emv=3.3uf see note 5 rstin_from_uc clkdiv2_from_uc clk track should be routed far from rst, i/o, c4 and c8. i/ouc_to/from_uc r1 rext1 see note 1 vdd c9 100nf external_clock_from uc c4 100nf c3 22pf aux1uc_to.from_uc see note 6 c5 10uf aux2uc_to/from_uc see note 3 see note 1 clkout_to_uc vdd clkdiv1_from_uc cmdvcc _from_uc 5v/3v_select_from_uc off _interrupt_to_uc r3 rext2 - or - see note 7 smart card connector 1 2 3 4 5 6 7 8 9 vcc rst clk c4 gnd vpp i/o c8 sw-1 sw-2 vdd l1 10uh cs_from_uc clksel_from_uc strobe_from_uc see note 2 notes: 1) vdd supply must be = 2.7v to 3.6v dc). 3) required if external clock from up is used.4) required if crystal is used. y1, c2 and c3 must be removed if external clock is used. 5) pin can not float. must be driven or connected to gnd if power down function is not used. 6) internal pull-up allows it to be left open if unused. 7) rext1 and rext2 are external resistors to ground and vdd to modify the vdd fault voltage. can be left open. 2) keep l1 close to pin 2. vdd r2 20k 10 card detection switch is normally closed. low esr (<100mohms) c1 should be placed near the sc connecter contact c8 c7 c6 27pf 27pf 27pf 8) capacitors c7 and c8 are optional. c6 is mandatory for nds. figure 11 : 73s8023c C typical application schematic downloaded from: http:///
73s8023c data sheet ds_8023c_019 18 rev. 1.5 12 electrical specification 12.1 absolute maximum ratings operation outside these rating limits may cause permanent damage to the device. parameter rating supply voltage v - 0.5 to 4.0 vdc dd input voltage for digital inputs - 0.3 to (v dd +0.5) vdc storage temperature - 60 c to 150 c pin voltage (except lin and card interface) - 0.3 to (v dd +0.5) vdc pin voltage (lin) - 0.3 to 6.0 vdc pin voltage (card interface) - 0.3 to ( v cc + 0.5) vdc esd tolerance C card interface pins +/ - 6 kv esd tolerance C other pins +/ - 2 kv esd testing on card pins uses the hbm condition, 3 pulses, each polarity referenced to ground. the smart card pins are protected against short ing between any combination of smart card pins. 12.2 recommended operating conditions p arameter rating supply voltage v dd 2.7 to 3.6 vdc ambient operating temperature - 40 c to +85 c input voltage for digital inputs 0 v to v dd + 0.3 v 12.3 package thermal parameters p ackage rating 32qfn 47 c / w (with bottom pad soldered) 32qfn 78 c / w (without bottom pad soldered) downloaded from: http:///
ds_8023c_019 73s8023c data sheet rev. 1.5 19 12.4 card interface ch aracteristics symbol p arameter condition min typ max unit card power supply (v cc ) dc - dc converter general conditions, - 40 c < t < 85 c, 2.7 v < v dd < 3 .6 v v card supply voltage including ripple and noise cc inactive mode - 0.1 0.1 v inactive mode i cc - 0.1 =1 ma 0.4 v active mode i cc 4.75 < 65 ma; 5 v 5.25 v active mode i cc 2.8 < 65 ma; 3 v 3.2 v active mode single pulse of 100 ma for 2 s; 5 v , fixed load = 25 ma 4.6 5 5.25 v active mode single pulse of 100 ma for 2 s; 3 v , fixed load = 25 ma 2.76 3.2 v active mode current pulses of 40 nas with peak |i cc 4.6 5 | < 200 ma, t < 400 ns; 5 v 5.25 v active mode current pulses of 40 nas with peak |i cc 2.76 | < 200 ma, t < 400 ns; 3 v 3.2 v v vcc ripple ccr 350 mv i maximum supply current to the card ccmax static load current v cc 100 > 4.6 or 2.7 v as selected, l=10 h ma i i ccf cc fault current 100 125 180 ma v v sr cc c slew rate C rise rate on activate f on v cc 0.05 = 1 uf 0.15 0.25 v/ s v v sf cc c slew rate C fall rate on de activate f on v cc 0.1 = 1 uf 0.3 0.5 v/ s c external filter capacitor (v f cc to gnd) 0.47 3.3 4.7 f l inductor (lin to v dd ) 10 h limax imax in inductor v cc = 5 v , i cc = 65 ma, v dd = 2.7 v 400 ma efficiency v cc = 5 v , i cc = 65 ma, v dd = 3.3 v 87 % downloaded from: http:///
73s8023c data sheet ds_8023c_019 20 rev. 1.5 1011b01 converter efficiency (vcc 5v) 50 55 60 65 70 75 80 85 90 95 100 0 20 40 60 80 100 icc [ma] efficiency [%] 2.7v 3.0v 3.3v 3.6v figure 12 : dc C dc converter efficiency (v cc = 5 v) output current on vcc at 5 v. input voltage on v dd 1011b01 converter efficiency (vcc 3v) 50 55 60 65 70 75 80 85 90 95 100 0 20 40 60 80 100 icc [ma] efficiency [%] 2.7v 3.0v 3.3v (linear) 3.6v (linear) at 2.7 , 3.0, 3.3 and 3.6 volts . figure 13 : dc C dc converter e fficiency (v cc = 3 v) output current on vcc at 3 v. input voltage on v dd at 2.7, 3.0, 3.3 and 3.6 volts . converter efficiency (v cc 3 v) converter efficiency (v cc 5 v) downloaded from: http:///
ds_8023c_019 73s8023c data sheet rev. 1.5 21 symbol parameter condition min typ max unit interface require ments C data signals: i/o, aux1, aux2, and host interfaces: i/ ouc, aux1uc, aux2uc. i shortl , i shorth , and v inact requirements do not pertain to i//ouc, aux1uc, and aux2uc. v output level, high (i/o, aux1, aux2) oh i oh = 0 1 0.9 v cc v cc v + 0.1 i oh 0.75 v = - 40 a cc v cc v + 0.1 v output level, high (i/ouc, aux1uc, aux2uc) oh i oh 0.9 v = 0 dd v dd v + 0.1 i oh 0.75 v = - 40 a dd v dd v + 0.1 v output level, low ol i ol =1 ma 0.3 v v input level, high (i/o, aux1, aux2) ih 1.8 v cc v + 0.30 v input level , high (i/ouc, aux1uc, aux2uc) ih 1.8 v dd v + 0.30 v input level, low il - 0.3 0.8 v v output voltage when outside of session inact i ol = 0 0.1 v i ol = 1 ma 0.3 v i input leakage leak v ih = v cc 10 a i input current, low (i/ouc, aux1uc, aux2uc) il v il = 0, cs = 1 0.65 ma v il = 0, cs = 0 5 a input current, low (i/o, aux1, aux2) v il = 0 2 ma i short circuit output current shortl for output low, shorted to v cc through 33 ? 15 ma i short circuit output current shorth for output high, shor ted to ground through 33 ? 15 ma t r , t output rise time, fall times f c l = 80 pf, 10% to 90%. for i/ouc, aux1uc, aux2uc, c l = 50 pf 100 ns t ir , t input rise, fall times if 1 s r internal pull - up resistor pu output stable for > 200 ns 8 11 14 k ? i puhiz pull - up current, hi - z state for pins iouc, aux1uc, aux2uc when cs = 0 5 a fd maximum data rate max 1 mhz t delay, i/o to i/ouc, i/ouc to i/o (falling edge to falling edge) fdio 100 started ns delay, i/o to i/ouc, i/ouc to i/o (rising edge to rising edge) 10 c input capacitance in 10 pf 1 nds applications require a 27 pf capacitor on i/o placed at the smart card connector. downloaded from: http:///
73s8023c data sheet ds_8023c_019 22 rev. 1.5 symbol parameter condition min typ max unit reset and clock for card interface, rst, clk v output level, high oh i oh 0.9 v = - 200 a cc v v cc v output level, low ol i ol 0 = 200 a 0. 2 v v o utput voltage when outside of a session inact i ol = 0 0.1 v i ol = 1 ma 0.3 v i output current limit, rst rst_lim 30 ma i output current limit, clk clk_lim 70 ma t r , t output rise time, fall time f c l = 35 pf for clk, 10% to 90% 8 ns c l = 200 pf for rst, 10% to 90% 100 ns td delay time strobe to clk, rstin to rst clksel = 1, cap. load on clk and rst is minimal, else rise, fall times are a factor 20 ns duty cycle for clk c l = 35 pf, 48% < in 45 < 52% 55 % 12.5 digital signals symbol parame ter condition min typ max unit digital i/o e xcept for osc i/o v il input low voltage - 0.3 0.8 v v ih input high voltage 1.8 v dd + 0.3 v v ol output low voltage i ol = 2 ma 0.45 v v oh output high voltage i oh = -1 ma v dd - 0.45 v r out pull - up resis tor, off 20 k ? t sl time from cs go ing high to interface active 50 ns t dz time from cs going low to interface inactive, hi -z 50 ns t is set - up time, control signals to cs rising edge 50 ns t si hold time, control signals from cs rising edge 50 ns t id set - up time, control signals to cs fall 50 ns t di hold time, control signals from cs fall 50 ns |i il1 | input leakage current gnd < v in < v dd -5 5 a downloaded from: http:///
ds_8023c_019 73s8023c data sheet rev. 1.5 23 symbol parameter condition min typ max unit oscillator (xtalin) i/o parameters v ilxtal input low voltage - xtalin - 0.3 0.3 v dd v v ihxtal input high voltage - xtalin 0.7 v dd v dd +0.3 v i ilxtal input current - xtalin gnd < v in < v dd - 30 30 a f max max freq. osc or external clock 27 mhz in external input duty cycle limit t r/f < 10% f in , 45% < clk < 55% 48 52 % 12.6 dc characteristics symbol parameter condition min typ max unit i supply current on v dd linear mode, icc = 0 i/o, aux1, aux2 = high dd 4.9 ma step up mode, icc = 0 i/o, aux1, aux2 = high 4.7 ma i supply current on v dd_pd dd pwrdn = 1, start/stop bit = 0 all digital inputs driven with a true logical 0 or 1 in power down mode 0.1 1 2 .5 a 12.7 voltage / temperature fault detection circuits symbol parameter condition min typ max unit v v ddf dd fault C v dd no external resistor on vddf_adj voltage supervisor threshold) 2.15 2.4 v v v ccf cc fault C v cc v voltage supervisor threshold cc 4 .20 = 5 v 4.6 v v cc 2.5 = 3 v 2.7 v t die over temperature fault f 115 145 c i card over current fault ccf 100 150 ma downloaded from: http:///
73s8023c data sheet ds_8023c_019 24 rev. 1.5 13 mechanical drawing (32 - qfn) 2.5 5 2.5 5 top view 1 2 3 figure 14 : 32 - qfn mechanical drawing 0.85 nom. / 0.9max. 0.00 / 0.005 0.20 ref. seating plane side view 0.2 min. 0.35 / 0.45 1.5 / 1.875 3.0 / 3.75 0.18 / 0.3 bottom view 1 2 3 0.25 0.5 0.5 0.25 3.0 / 3.75 1.5 / 1.875 0.35 / 0.45 chamfered 0.30 downloaded from: http:///
ds_8023c_019 73s8023c data sheet rev. 1.5 25 14 package pin designation (32 - qfn) use handling procedures necessary for a static sensitive component. (top view) figure 15 : 32 - qfn 73s8023c pin out 6 7 8 9 5 4 3 2 1 17 18 19 20 2423 22 21 1011 12 13 14 15 16 32 31 3029 28 27 26 25 gnd lin vdd nc prdwn pres pres i/o xtalout xtalin off gnd vdd rstin cmdvcc vddf_adj aux2 aux1 gnd clk rst vcc clksel teridian 73s8023c strobe clkout 5v/3v clkdiv2clkdiv1 aux2ucaux1uc i/ouc cs downloaded from: http:///
73s8023c data sheet ds_8023c_019 26 rev. 1.5 15 ordering information part des cription order n umber packaging mark 73s8023c - qfn 32 - pin lead - free qfn 73s8023c - im/f 73s8023c 73s8023c - qfn 32 - pin lead - free qfn tape / reel 73s8023c - imr/f 73s8023c 16 related documentation the following 73s8023c documents are available from teridian semiconductor corporation: 73s8023c data sheet (this document) 73s8023c qfn demo board users guide 17 contact information for more information about teridian semiconductor products or to check t he availability of the 73s8023c, contact us at: 6440 oak canyon ro ad suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: scr.support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . downloaded from: http:///
ds_8023c_019 73s8023c data sheet rev. 1.5 27 revision history rev ision date description 1.0 6/13/2005 first publication. 1.1 7/15/2005 converted to teridian format. 1.2 12/5/2007 add emv and iso logo, remove leaded package option, change 32qfn punched to sawn package. 1.3 1/17/2008 changed dimension of bottom exposed pad on 32qfn mechanical package figure. 1.4 1/8 /2009 added nds logo to page 1 and assigned document number. 1.5 4/3 /2009 remove d all references to vpc as vpc must be tied to vdd. ? 2009 teridian semiconductor corporation. all rights reserved. teridian semiconductor corporation is a registered trademark of teridian semic onductor corporation. simplifying system integration is a trademark of teridian semiconductor co rporation. all other trademarks are the property of their respective owners. teridian semiconductor corporation makes no warranty for the use of its produc ts, other than expressly contained in the companys warranty detailed in the teridian semiconductor corporati on standard terms and conditions. the company assumes no responsibility for any errors which m ay appear in this document, reserves the right to change devices or specifications detailed he rein at any time without notice and does not make any commitment to update the information contained herein. ac cordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon rd., suite 100, irvine, ca 92618 tel (714) 508 - 8800, fax (714) 508 - 8877, http://www.teridian.com downloaded from: http:///

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